In a storage device, for example, a logical volume is divided into unit areas for each 128 logical block addressing (LBA), a cache area is divided into blocks for each 128 LBA, and a cache bundle element (CBE) which manages the block in the cache area is prepared. When there is an access to the logical volume from a higher rank device, the CBE is allocated for each unit area in the logical volume including an access destination area and the block in the cache area is associated with the CBE.
In the related art, for example, a direct memory access unit accesses a cache memory to determine a cache hit or cache miss while a processor stops. In addition, for example, there is technology in which each processor package has an ownership of each logical device and divides an input/output command from a host device that designates an address spanning a division position in one logical device to share input/output processing in a plurality of processor packages.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2000-082011 and International Publication Pamphlet No. WO 2015/056332.